To work independently on Standard Cell layout design from schematics with minimal support from seniors.
Hands on exp in Standard Cell Layout design.
Good understanding of deep sub-micron and DFM issues and layout techniques.
Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc.
Working knowledge of layout design and physical verification tools Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
Responsible for timely and quality execution of layout design.