We are looking for an energetic and enthusiastic Engineer who has passion to build reusable and structured
verification environments . This position is based in Bangalore. As a team we have culture of continuous
development and we challenge ourselves on an ongoing basis for further improvement . We offer a great environment to get exposed to a wide range of
technology. Our team works closely with Architecture, Marketing, Product Engineering, and Software teams to deliver on time quality verification.
Work independently with Design, architecture and systems teams to translate functionality into verification plan and drive verification to closure.
Innovate on Verification methodologies and deploy them across team to automate flows to save time and effort.
Create reusable block/chip level environments using UVM (system verilog).
Deploy latest verification tools across team (such as formal) to augment verification.
Support post silicon debug.
Support junior team members and provide technical leadership to team.
Good exposure to SOC architecture , verification methodologies and flows.
Expertise in constraint random verification methodology using UVM and System Verilog.
Should have experience in developing VIPs/Environments from scratch.
Experience in translating functional specification to test plan and driving it to closure.
Very good understanding on Verilog expected, VHDL knowledge is plus.
Good knowledge in gate-level simulation, and Scripting languages ( Perl and Shell)
Ethernet Domain knowledge (IEEE 802.3) is plus
Knowledge of Ethernet L2 network protocols is a plus
Strong debugging and problem solving skills.
Should have a passion to learn and deploy new methodologies.