Sta/synthesis/sr. Engineer/lead

Ikya Human Capital Solutions Pvt Ltd
  • Bangalore
  • 10-20 lakh
  • 5-10 years
  • Views
  • 04 Oct 2016

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Experience in synthesis of complex SoCs block/top level and writing timing constraints
Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints
Experience in post-layout STA closure and timing ECOs
Worked in technology nodes 45nm and below
Knowledge of low-power aware implementation is a plus
Tools: RTL Compiler, LEC, CLP, ETS/PTSI/GT

Competencies/Skill sets for this job

Timing Constraints Ptsi Socs Synthesis Verification Constraints Netlist

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