Analog Layout Engineer .
Experience in CMOS process technologies 10nm,14nm,16nm, 22nm, 28nm, etc.
Expertise in understanding circuits and Layout of Analog Block such as Pipeline ADC, LDO, PLL, Reference Generators.
Experience in Debugging DRC, DFM, LVS, Antenna.
Expertise in deep sub micron process till 14nm FinFET, CMOS, FDSOI and BICMOS technologies.
Hands on Layout design and verification of multiple Analog blocks in RFIC chip.