Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm)
Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage
Experience in Cadence SoC Encounter EDA Tool flow is required.
At least 2 Full Chip T/O experience for 8 years experienced engineers
Desirable: Multi-million gate low-power designs