Senior Physical Design Engineer

Sankalp Semiconductor Pvt. Ltd.
  • Bangalore
  • Confidential
  • 6-8 years
  • Views
  • 27 Oct 2016

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description


Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm)
Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage
Experience in Cadence SoC Encounter EDA Tool flow is required.
At least 2 Full Chip T/O experience for 8 years experienced engineers
Desirable: Multi-million gate low-power designs


Competencies/Skill sets for this job

IP USB Design Engineering Physical Design

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Sankalp Semiconductor Pvt. Ltd.