Candidate would be required to work on various phases of SoC timing closure activities
Constraint development, timing mode identification & definition, timing closure with SI,
noise closure and signoff timing at block and chip level. Also need to work on Synthesis,
equivalence checks, timing & functional ECO implementation and power optimization.
Candidate should have in-depth knowledge of STA concepts. Should be well experienced
in various aspects of STA Constraint definition, Timing closure, noise analysis and
power optimization. Should be well versed with Synthesis, equivalence checks, timing &
functional ECO implementation. Should have worked on atleast 2 tapeouts.
Expertise in scripting languages such as perl, shell, TCL, etc. is an added advantage.
Experience with tools such as PrimeTime, design compiler, Formality, LEC and Spyglass
is highly desirable. Knowledge of UPF would be an added advantage.
Should possess excellent problem solving skills.
Should be able to work independently and help other team members.
Should be experienced in working in a global team and dynamic environment.
Should possess ability to learn and adapt to new tools and methodologies.
Should possess good communication skills.