RTL Design Engineers
ASIC Flows LINT CDC DRC rule checking & Synthesis using RTL compiler
Micro-architecture and RTL implementation
Block level/ full chip integration and design.
3+ years experience with design, verification and timing tools .
Hands-on with Lint, CDC, LEC preferably Low Power check tools
Some experience of AXI/AHB
design in System Verilog and timing, performance & power optimizations
Good understanding of design implementation flows and tools (Synthesis, STA, and DFT).
Knowledge of configuration tools and workflow tools: Clearcase/ClearQuest
Scripting experience - Perl or Tcl
CPU and debugging experience
#2. Verification Engineers
Experience in C Based & SOC (System level) verifications
Define and develop verification architecture
Proficient in HDL (Verilog/VHDL/System Verilog), Test bench Methodologies(UVM)
Define and develop verification environments
Write verification specifications, verification plans, and documentation
Generate test bench and automatic regression plans
Responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs (schematics, analogue, RTL)
Complete block-level verification and chip level verification
Debug tests, run gate level simulations at unit/sdf delays
Project experience with leading edge verification methodologies like OVM/UVM
Project experience in coverage/assertion driven verification
Advanced skills in various programming languages including Verilog, System Verilog, C, C++, PERL, TCL.