You have hands on expertise in various phases of SoC physical design activities like floor-planning, partitioning,
placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).
You have Full chip tapeout experience based on 28nm/16nm and lower technologies.
You are extremely good in layout activities both at block and SoC level.
You have excellent problem solving skill to help through congestion resolution and timing closure.
You have expertise on formal verification and timing analysis and Eco implementation.
You are experienced in working in a global team and dynamic environment.
You have exceptional interpersonal and communication skills.
You have the ability to adapt, be creative, and learn more.