Physical Design Engineer

Bee5 Manpower Consulting
  • Bangalore, Hyderabad, Pune
  • 10-16 lakh
  • 4-9 years
  • Views
  • 28 Mar 2017

  • IT/ Information Technology

  • Electrical/ Electronics
Job Description

Perform top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks(DRC), and Logical vs. Schematic (LVS) checks, antenna checks.
Expertise and sound knowledge in Cadence/ Synopsys or Magma Physical Design Tools and standard backend tool flows is a must
Hands-on with scripting languages such as PERL, TCL strong physical verification skill set.
Perform static timing analysis in Primetime or Primetime-SI.
Should have worked on 65nm or lower node designs with advance low power techniques such as voltage islands, power gating and substrate-bias.
Experience in backend flow including physical design, timing analysis to final tape out in 28nm and below.
Knowledge and previous experience in full chip physical design, Low Power Design - Voltage islands, power gating, substrate-bias techniques is desirable
Competencies in timing closure on DDR2/DDR3/PCIE interfaces will be of advantage.
Expertise in Physical Design performing top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks(DRC), and Logical vs. Schematic (LVS) checks, antenna checks.
Must have a valid Passport valid for minimum 2 Years.
Expertise and sound knowledge in Cadence/ Synopsys or Magma Physical Design Tools and standard backend tool flows is a must
Hands-on with scripting languages such as PERL, TCL strong physical verification skill set.
Ability to perform static timing analysis in Primetime or Primetime-SI.
Rich experience on 65nm or lower node designs with advance low power techniques such as voltage islands, power gating and substrate-bias.
Sound knowledge of backend flow including physical design, timing analysis to final tape out in 28nm and below.
Knowledge and previous experience in full chip physical design, Low Power Design - Voltage islands, power gating, substrate-bias techniques is desirable
Competencies in timing closure on DDR2/DDR3/PCIE interfaces will be of advantage.


Competencies/Skill sets for this job

Perl Magma Timing Analysis Routing Power Gating

Job Posted By

About Organisation

Bee5 Manpower Consulting