Experienced in deep submicron effects and low power implementation using UPF/CPF.
knowledge in Perl and TCL.
Cadence implementation tools (Genus, Innovus, Tempus) and Calibre physical verification for DRC/LVS.
Be responsible for Timing constraint development, Synthesis, DFT, generation/optimization of pad rings, full chip floor-planning and partitioning with power domains, clock tree synthesis, power and IR drop analysis and final timing closure.
Be responsible for Power-aware implementation flow, including UPF/CPF and verification using Conformal Low Power.