Responsibilities: Architect and develop or adapt an existing PHY to create a low power, multi-protocol SerDes IP for Networking, Storage and Consumer Applications. Duties include design and supervision of various critical blocks such as PLLs, High Speed I/Os and CDRs. The engineer will also be responsible for defining design for test strategies for the Serdes IPs.
Education: Masters degree in Electrical or Electronics Engineering
Experience: Minimum 10 years experience in high performance analog circuit design.
Knowledge and experience of PLL and CDR design in deep-submicron CMOS nodes
Experience with the architecture, design and silicon validation of Serdes up to 10Gbps .
Knowledge of Matlab/VerilogA/ Verilog AMS modeling of PLL and CDR architectures
Understanding of digital connectivity interfaces like PCI-Express, USB, Display Port/ HDMI