Design Verification & Validation Engineer - Esterline Technologies

Esterline Technologies India Pvt Ltd
  • Bangalore
  • 10-15 lakh
  • 4-8 years
  • Views
  • 28 Sep 2016

  • IT/ Information Technology

  • Aviation/ Airlines
Job Description

Key Duties : As a Lead - Design Verification Engineer, responsibilities include :
Develop PLD/FPGA Verification environment and process applying DO-254 guidelines.
Verification of RTL Design (DO254 Level A/B) and complex FPGA modules comprising a mix of custom RTL with hard and soft vendor IP cores within a larger Architecture, using methodologies such as
a) Code Review, pre-synthesis(Functional Simulation, Post synthesis simulation, Post Layout simulation and Physical Verification).
b) Develop unit/core/system level test bench(VHDL), BFMs (Bus Functional Models), checkers and assertions using verification standard methodologies.
c) Interface with the architecture/design team to develop and execute test plans.
d) Writing directed and random test cases, debugging failures, filing and closing bugs.


Competencies/Skill sets for this job

RTL Design FPGA

Job Posted By

Pallavi Ranganath
Talent Acquisition - Human Resources