Design Engineer

Macropace Technologies
  • Bangalore
  • 10-14 lakh
  • 2-7 years
  • Views
  • 17 May 2017

  • Design

  • Electrical/ Electronics
Job Description

- Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 2+years of recent work
experience, worked on passing test cases, test benches, Building environment.

- Knowledge of Functional coverage using HVL language features or assertions a plus.

- Good Knowledge Gate Level Simulations

- Should be ARM based SoC verification only. No need to mention tools.

- Proficiency in one scripting language like ,Perl, C/C++,


Competencies/Skill sets for this job

Perl Soc Verification Chip Verification

Job Posted By

About Organisation

Macropace Technologies