4+ years of design verification experience
3+ years of OOP coding experience (VERA, System Verilog) and SV Assertions
Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM
Strong working experience in areas like DFT/MBIST/Scan Clear/LBIST/Boundary Scan.
Familiarity with Verilog and General Logic Design concepts
Knowledge of system-level architecture including buses like AXI/AHB, bridges, AXI interconnects.
Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
Experience using UNIX Revision Control tools - Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla and JIRA
Experience in verifying multimillion gate chip designs from specifications to tape-out
Excellent communication and presentation skills
Demonstrate the ability to work with cross-functional teams
Familiarity with processors and boot flow would be useful
Familiarity with Software development flow including assembly and C is beneficial