DFT Engineer

Sankalp Semiconductor Pvt. Ltd.
  • Bangalore
  • 10-20 lakh
  • 3-5 years
  • Views
  • 27 Oct 2016

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Responsibilities include:
- In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis.
- Analyze design and propose best compression technique.
- Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed.
- Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques.
- Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus.
-In depth knowledge and hands on experience in MBIST insertion and Memory test validation. Expertise in Mentor tools is plus.
- Hands on experience on JTAG boundary scan (IEEE 1149.1, 1149.6 ) is plus.
- Work with IDDQ constrains, validation, and pattern generation.
- Owns STA constraints and work with STA team to resolve timing violations
- Experience in RTL and Gate level simulations of scan and MBIST test vectors.
- Expertise in scripting languages such as perl, shell, etc.
-Ability to work with global teams.
-Ability to learn and adapt to new tools and methodologies.
-Ability to do multitasking & work on several high priority designs in parallel.
-Excellent problem solving skills
-Excellent communication and team work skills


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Sankalp Semiconductor Pvt. Ltd.