To work independently on Analog layout design of block level and chip level from schematics.
Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc.
Good understanding of deep sub-micron and DFM issues and layout techniques.
Should have work experience in CMOS process technologies - 22nm, 28nm, 45nm, 65nm etc.
Thorough working knowledge of layout design and physical verification tools Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
Responsible for timely and quality execution of layout design.
Domain experience covering Voltage Regulators, BGs, PLLs, ADCs, DACs, High Speed Serial IOs like LVDS, HDMI, Display Port, PCIe, USB, DDR, etc
Must have been involved in the tasks like Floor Planning, Power Grid Planning, Area estimate for a given schematic, extracted Netlist generation for PLS
Proficient in DRC, LVS, DFM, ERC, Density cleanup and also worked on reliability checks like IR Drop, EM, Ipeak, ESD & Latchup etc
Experience in deep submicron technologies, down to 14nm FinFET technology, strongly desired.
Experience in LEF, FRAM view generation and documentation of the DRC,LVS,ERC results with waivers as per requirements
Work on Synopsys ICC based tools to fix DRC,LVS is a plus.
Layout Automation of verification tasks with command in Shell, Perl scripting highly desired.