ASIC Design Engineer- Rtl/verilog

Catalyst Solutions
  • Bangalore
  • 10-15 lakh
  • 5-10 years
  • Views
  • 20 Apr 2017

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

- Responsibilities may include, but are not limited to :

- Create transistor level designs of circuits to meet specifications

- Verify designs using circuit-level and behavioural-level simulations

- Supervise circuit layout

- Write circuit documentation

- Validate circuit performance in the lab

- Intuitive and analytical understanding of system level specifications.

- Strong written and verbal communication skills

- Good knowledge of verilog HDL language and RTL coding techniques with DFT skill is a must.

- Strong technical background in SOC/block-level design and verification with ability to do hands-on work involving RTL design, STA, LEC, LINT and CDC checks.

- Experience in code review, linting, constraint generation and support for integration is a must.

- Must have experience in generating block level synthesis and timing constraints for chip level.

- Strong knowledge of perl/awk/shell/tcl script is required

- Experience with System Verilog/UVM, Wreal coding is a plus.


Competencies/Skill sets for this job

Perl Documentation Verification Hands-on Coding Lint

Job Posted By

Sudeep V
Team Integrator

About Organisation

Catalyst Solutions