Minimum 12 years of exp in ASIC Design Verification at both block & SoC level.
Excellent hands-on debug skills.
Exp in Wireless SOCs / SubSystems is highly desired.
Must have excellent knowledge of SoC verification flows
Proficient in using modern constrained-random verification techniques like System Verilog, VMM / UVM.
Exp in developing complex test bench/model in UVM.
Responsible for verification at SoC level of mobile platforms