Technical Lead - IP Front End Design

  • Hyderabad
  • Confidential
  • 9-12 years
  • 01 Sep 2015

  • Project/ Program Management IT

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor, Electrical/ Electronics
Job Description

Candidate should have Masters Degree in Electronics / Electronics and Communication Engineering with 9-12+ years of experience.

Experience in Computer-Vision, Graphics and/or Image Processing & IP Design is must.

Expertise in IP Architecture, Specification Development, RTL coding is must.

Experience to timing analysis, IP level DFT implementation, RTL coding rules .

Experience in front-end design, verification and implementation tasks such as Synthesis, SDC development, Scan-Insertion, Formal Verification, ECO Implementation is desirable.

Experience with OpenCV libraries and/or development of Image-Processing and/or Computer-Vision algorithms with OpenCV is a plus.

Experience in RTL design in Verilog and Verification is must. Familiarity to System Verilog / UVM for verification is desired.

Experience in C/C++/System C and OpenCV modeling is desirable.

Familiarity to System Verilog / UVM for verification is desired.

Work with Physical Design team on floor-plan, budgeting, timing-closure, signal-integrity, ECO-flows, power-analysis etc.

Work with systems team during design bring-up on silicon or FPGA platform

Ability to work well with global teams and independently drive issue closure.

Should be able to lead a team/project and provide technical mentoring and guidance to junior engineers

Strong analytical ability, problem solving and communication skills.

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