Requirements/Qualifications (Education) : Bachelor/Masters in Electrical/Electronics Engg
External Job Description : Responsibilities :
1) Lead or contribute significantly towards Design and Development of Single/Multiport SRAM, ROM,CAM compilers in 40nm/28nm Technologies
2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder.
3) Interaction with fab regarding bitcell schematic/layout approval.
4) Development of critical path to perform detailed margin and characterization simulations to address various Memory Compiler Options including Power Gating,LS,DS
5) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
6) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
7) Logic simulations and detailed timing analysis of key paths in high speed memory design.
8) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.
9) Work with engineers working in wide areas: modeling, layout, compiler, Verification/Char to develop Memories that can correlate well with Silicon
1) Expertise of high speed/low power CMOS circuit design , clocking scheme, Static and dynamic logic circuits
2) Experience in Designing and Driving one or more Memory Compilers from Specifications final Silicon qualification in 40nm or below technologies
2) Complete hands on experience in using Cadence/Mentor schematic/layout editor tools
3) Complete hands on experience with Circuit simulation and waveform viewer tools such as HSPICE, HSIM, Nanosim, Turbowave etc
4) Knowledge of Verilog is Plus.
5) Knowledge of industry standard modeling formats such as .lib (liberty), CCS, NLDM is plus.
6) Experience in Skill/Perl/Python Scripting is a strong plus
7) Experience in Understanding the layout design issues in sub nanometer regime is a Plus