Perform sub-system and full-chip verification using Verilog / system-Verilog object oriented tests using UVM.
Develop verification environments, test benches and verification components (VIP)
Verify design implementation by developing test benches an
Collect and report verification coverage meeting specific coverage and milestone targets
Support the development of a flexible & reusable automated simulation/regression flow using Perl & Shell scripts for simulations.
Support the verification project