experience with floor-planning, clock distribution, power distribution,
timing-driven place and route, timing analysis, power/signal integrity
analysis, test insertion, and physical verification
Delivered several sub-micron ASIC tapeouts. Experience closing a physical design (timing, noise, EM/IR) in low power designs.
Expertise on Cadence EDI and ETS, particularly ETS
Knowledge of scripting languages like PERL/TCL/Skill
Knowledge of Synthesis, DFT and STA is a plu
Excellent communication and presentation skills