Bachelor degree in Electronics mainstream and 3+ years experience in Analog layout.
Experience in analog, mixed-signal layout, including designs of PGAs, ADC, DAC, PLL, SerDes Rx/Tx.
Knowledge in basic circuits, matching constraints, design-driven constraints expected according to experience level.
Standard analog layout techniques and good understanding of physical, electrical aspects of layout.
Experience with IP release, chip-level assembly and chip tapeout procedures.
Good understanding of reliability physics including Electro-migration, ESD and Latchup.
Experience with 40nm and/or 28nm technologies and their device physics highly desirable.
Proficiency with industry-standard layout and verification tools in a Linux environment Cadence: Virtuoso IC6.1, Assura; Mentor: Calibre.
Experience in RF layouts and techniques will be added advantage.