Physical Design (floor Planning /timing Closure /power Planning/io pla

Talent HR Solutions
  • Bangalore
  • 10-15 lakh
  • 5-10 years
  • 01 Sep 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

1.Working Knowledge on Sytnhesis /Place and Route(PnR),CTS /Floor Planning /Timing closure /Power Planning/IO planning Core timing /IO Timing closure2.Have lead atleast 3 tapeouts in complete flow of Physical Design.3. Should have worked with ARM
1 .Exposure to MAGMA,ICC,Primetime,PTSI,Design Compiler,Apache,Calibre .2. Should be able to handle some full chip level activities.

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