1.Working Knowledge on Sytnhesis /Place and Route(PnR),CTS /Floor Planning /Timing closure /Power Planning/IO planning Core timing /IO Timing closure
2.Have lead atleast 3 tapeouts in complete flow of Physical Design.
3. Should have worked with ARM
1 .Exposure to MAGMA,ICC,Primetime,PTSI,Design Compiler,Apache,Calibre .
2. Should be able to handle some full chip level activities.