B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering
Minimum 3+ years experience in ASIC Design Verification , with knowledge of Computer Architecture
Experience in any compute architecture such as x86 or ARM domain based SOCs/Cores.
OVM/UVM Methodology knowledge and experience is a plus
Must have excellent knowledge of Core design & verification flows
Experience in developing complex test bench/model in Verilog, System Verilog or SystemC
Experience in writing test plans and test cases
Excellent hands-on debug skills
Strong Verilog, System Verilog, PLI/DPI interface, SystemC or C/C++, Perl/shell script programming skills.
Must have good communication skills and the ability and desire to foster a team environment.