Physical Design Engineer/lead

Allegro Solutions
  • Bangalore
  • 10-15 lakh
  • 4-9 years
  • 12 Mar 2015

  • IT/ Information Technology

  • IT/ Technology - Hardware & Networking
Job Description

Key Qualifications:

- The ideal candidate will have 5+ years of physical design experience, with recent successful tapeouts in deep submicron technologies (45nm and below).Strong knowledge of Full chip floor planning, partitioning and Detailed PD Flow.

- Proven ability to handle team with respect to Block to full chip floor plan.

- Proven ability to execute to stringent schedule and Strong communication skills with following responsibilities,

- Block level and Full Chip Floor planning, Metal Layer estimation-planning, power planning, Full Chip Signoff closure.

- You will also be responsible for driving methodology development, automation, collaborate with other design teams, share best practices followed.

- Work independently and with multisite teams in the areas of RTL to GDSII implementation with focus on Floor planning.

- Interact with various team comprising of block build, Design automation(CAD) and design technology teams to resolve various issues in timely manner.

- Experienced in Synopsys ICC or EDS (SoCEncounter) tools used and their capabilities & underlying algorithms .

- Sound expertise in Tcl, Perl, Shell scripting

- Needs to work from customer site in the US during requirements of Project kick off, mid reviews and hand over.

Technical Skill [Required]:

- Synopsys ICC, OR EDS/SoC Encounter

- Taking care of full chip SOC PD issues (including block and full chip floor planning, Flow development, Timing sign off, at 65, 45, 28nm and below.

- Qualification: BE/B.Tech/ME/M.Tech

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Allegro Solutions