4~6+Yr+ exp on digital design (Architecture, RTL coding, Integration, Synthesis, LEC, STA , DFT, Low power, FPGA. Good understanding & coding skill in Verilog, Perl & TCL. Experience in ASIC flow with front-end design and integration to Tapeout.
Strong knowledge of ASIC / FPGA design methodology & should be well versed in front-end design, simulation & synthesis tools. Good understanding and hangs on experience of Protocols such as AMBA AXI, AHB, APB, OCP, LPDDR2.