Wireless Connectivity Design Verification Engineer

Brainsearch Consulting
  • Bangalore, Delhi, Hyderabad
  • 14-24 lakh
  • 4-9 years
  • 29 May 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

4~10+ yar+ experiences on full chip verification for SoC platform.
Good understanding & coding skill in SystemVerilog, Verilog & also C/C++. Familiar with ARM based architecture from system architecture, instruction set & also memory subsystem
Exp in developing assertion based coverage driven constraint random verification methodologies eg UVM / VMM / OVM etc.
Expin SoC verification of different modules of connectivity combo chips. Low power verification using UPF/CPF, CLP, MVRC or NLP

Job Posted By

Mandeep M
Account Manager

About Organisation

Brainsearch Consulting