4~10+ yar+ experiences on full chip verification for SoC platform.
Good understanding & coding skill in SystemVerilog, Verilog & also C/C++. Familiar with ARM based architecture from system architecture, instruction set & also memory subsystem
Exp in developing assertion based coverage driven constraint random verification methodologies eg UVM / VMM / OVM etc.
Expin SoC verification of different modules of connectivity combo chips. Low power verification using UPF/CPF, CLP, MVRC or NLP