STA (static Timing Analysis) Design Engineer/lead Engineer

  • Bangalore
  • 10-15 lakh
  • 4-9 years
  • 21 Jul 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

looking for experienced Timing Analysis & Sign-off experts for IPs and complex digital subsystems. The engineer will be responsible for owning & working with a global team on sign-off criteria development, sign-off methodology development on latest nanometer technologies
Drive timing sign-off criteria for designs in latest technology nodes, 28nm and below
Lead in the area of signal integrity, margin development
Interact with a geographically distributed team of experts
Be hands-on technical individual contributor

Experience in Static Timing Analysis, sign-off criteria development
Expert in industry standard timing analysis methodology and tools like PrimeTime (Synopsys)
Familiar with Simulation to Silicon correlation, library char, derate development etc
Understands all aspects of PTV variation, AOCV
Good in TCL/Perl/Shell scripting
Circuit design experience is a plus
Binning experience is a plus
Masters in education is plus
Open for short travel

Key words :
1. STA, SSTA, OCV, Margins, Derates, Sign-off derate, PTV variation, sign-off criteria, STA methodology, sign-off methodology, binning
2. Tools PrimeTime, HSPICE, SPICE

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