Mandatory Skills :
Synthesis ,LEC,Place and Route(PnR),CTS,Floor Planning, Timing closure, Power Planning,IO planning Core timing , IO Timing closure, Constraints development
Should be comfortable with both implementation and signoff tools
Desired Skills :
MAGMA,ICC, Primetime ,PTSI,Design Compiler,Apache,Calibre
Should be able to handle some full chip level activities. Block (Medium complexity) level PD engineer
Have lead at least 3 tape outs in complete flow of Physical Design.
Should have worked with ARM processor at SoC level.