Experience implementing complex IP/ASIC Physical Design, experience with SoC floorplan/padring/placement/cts experience.
Technical hands-on capability and strong related P&R experience. Preferably Synopsys flows/tools
He/She should have experience in complete block level implementation (2M plus) and top level integration experience or MACRO implementation experience
Similar company work experience
Has implemented large blocks with more than 30% area with memories.
Good at design closure (congestion, timing and physical verification)
Exposure to multi-million gate design (>2million instances with 100+ memories) in recent technologies (32nm,28nm,20nm). Desired experience using Synopsys ICC with good TCL scripting skills
Timing : should be able to drive the timing closure, constraints definition/cleanup. Desired experience using Synopsys PT
Integration/Physical Verification: desired chip finish experience using Mentor Caliber for DRC/LVS, handling multi-million hier designs, along with good understanding of the sign-off checks, EM/IR, XTalk, DFM
Willing to travel for short duration if needed.