Leading and participating in Modem SubSystem level verification as a senior member of the team.
Being a mentor and technical leader for more junior verification engineers.
Responsible for verification at SoC level of mobile platforms
Creating test plans for verification of the various features and test plan execution using constrained random verification strategy
Develop verification components using UVM/VMM and System Verilog
Actively participate in the architectural discussions and provide feedback to RTL as needed
Desired Skills and Experience
B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering
Minimum 12 years of experience in ASIC Design Verification at both block and SoC level
Excellent hands-on debug skills
Proficient in using modern constrained-random verification techniques like System Verilog, VMM/UVM. Experience in developing complex test bench/model in UVM
Experience in Wireless SOCs/SubSystems is highly desired.
Must have excellent knowledge of SoC verification flows
Experience on industry standard simulation tools
Excellent multi-tasking skills
Should have good communication skills and the ability and desire to foster a team environment