Exp implementing complex IP/ASIC Physical Design, exp with SoC floorplan / padring / placement / cts exp. Technical hands-on capability & strong related P&R exp.
Pref Synopsys flows/tools.
Good at design closure (congestion, timing & physical verification.
Good at design closure (congestion, timing & physical verification) Exposure to multi-million gate design (>2million instances with 100+ memories) in recent technologies (32nm,28nm,20nm.
Desired exp using Synopsys ICC with good TCL scripting skills