Job Description :
Experience implementing complex IP/ASIC Physical Design
Preferably 3 to 12+ years experience with SoC floorplan/padring/placement/cts experience.
Technical hands-on capability and strong related P&R experience. Preferably Synopsys flows/tools
Has implemented large blocks with more than 30% area with memories
Exposure to multi-million gate design (>2million instances with 100+ memories) in recent technologies (32nm,28nm,20nm...). Desired experience using Synopsys ICC with good TCL scripting skills
Desired experience using Synopsys PT