(1) Implementation of multimillion gate SoC designs in cutting edge process technologies (65nm, 40nm, 28nm& below ).
(2) Strong Hands-on expertise on any of the aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floor plan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tape out.
(3) Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required. Understanding of process variation effects, and experience in variations analysis/modeling techniques and convergence mechanism would be a plus.
(4) Expertise in Synopsys IC compiler, Magma or Cadence SOC encounter physical design tools.
(5) Skill and experience in scripting using Tcl or Perl is highly desirable.