Creating the top level verification plans in collaboration with peer engineers
Verliog and one of verilog- A or Verilog- AMS or System Verilog or Specman
Advanced Verification methodologies such as UVM, ERM, VMM or VERA.
Closed-loop simulation with digital design and analog behavioral models and or transistors
Mixed -singal AMS experience using the Cadence-based Solution (irun+specture or irun+ultrasim etc.)
Experience with I2C, SPI, EMV, USB, or MIPI protocols
High power DC- DC buck Converters.
Educational Qualification : B.E or B. Tech / M. E
Experience : B.E or B. Tech 5 yers / M. E 3yrs
Skill Set : Should have sound knowledge in Mixed Signal Semiconductor designs, IC Products, IC Chips.