Masters in Engineering/ Bachelors in Engineering from a reputed institute (Tier 1 or Tier2 Colleges) with good academic record (min 70%)
8 - 14 years of experience in SoC / ASIC design
External Job Description : Job profile:
Architecture, design and RTL coding of Block level and chip level RTL development
Worked on complex data path designs and/ IP development
Participate in DFT insertion and integration of SoCs.
DFT audits and signoff
Participate in synthesis and timing analysis
Required knowledge and skills:
VLSI Design flows
Logic and Circuit design
Expertise in Verilog
Synthesis and timing analysis
DFT insertion in multi clock, rail and high speed designs.
Expertise in DFT methodology, flow and tools
Test vector generation and ATE test vector debug
Good communication skills
Outstanding analytical and critical thinking skills.
Worked on complex data path designs and/ IPs
Knowledge of power analysis tools
Expertise in scripting languages
Knowledge of DFT Tetramax tool