Candidate is expected to work on RTL to GDS optimizing the implementations for power, timing & area
Be responsible for & own all aspects of physical design & physical verification effort at a block level.
Develop,support & maintain physical design flows & methodologies
Experience in PTSI, ICC/First Encounter/EDI, Nanoroute, Calibre, StarRC, & Conformal
Good knowledge of standard cell libraries
Hands-on with STA, EM/IR & sign-off flows
Hands-on experience with:
1. Floor planning, place & route, power & clock distribution, pin placement & timing constraints generation.
2. Timing convergence using high speed design techniques
3. Physical design verification.
4. Functional verification at various levels of design hierarchy with respect to golden RTL by formal methods.
Prior experience with 40nm or finer geometries